The Ultimate DataFlow for Ultimate SuperComputers-on-a-Chip, for Scientific Computing, Geo Physics, Complex Mathematics, and Information Processing
Veljko M. Milutinović, Erfan Sadeqi Azer, Kristy Yoshimoto, Gerhard Klimeck, Miljan Djordjevic, Miloš Kotlar, Miroslav M. Bojović, Bozidar Miladinovic, Nenad Korolija, Stevan Stanković, Nenad Filipović, Zoran B. Babovic, Miroslav Kosanić, Akira Tsuda, Mateo Valero, Massimo De Santo, Erich J. Neuhold, Jelena Skoručak, Laura Dipietro, Ivan Ratković · 2021
This paper introduces a conceptual 100BillionTransistor (100BT) SuperComputers-on-a-Chip consisting of N big multi-core processors, 1000N small many-core processors, and two hardware accelerators - an ASIC TPU-like fixed-structure systolic array accelerator and a FPGA based flexible-structure re-programmable accelerator for bandwidth-bound and latency-critical Machine Learning applications respectively. The proposed SuperComputers-on-a-chip concept requires interfaces to specific external accelerators based on Quantum, Optical, Molecular, and Biological paradigms (programmable using EnergyFlow programming models - Energy Flow also representing a concept introduced in this paper) but these issues are outside the scope of this article. Keywords - Accelerators, Big Data, ControlFlow, DataFlow, ManyCore, Machine Learning, MultiCore, Systolic Array