Hardware System for Parallel Processing of Flash Memory Chips for Preparing an Identification System
Sergey S. Vladimirov, A. Yankovskiy · Telecom IT · 2020
Research subject. The paper presents options for the implementation of a hardware-software system for parallel processing of flash memory chips for preparing an identification system. Method. The analy-sis of the degradation rate of memory modules is carried out and the average values of the processing time and the number of processing cycles for one memory chip during the preparation of the identifier are determined. Core results. Parallel and serial-parallel schemes for flash memory chips processing are proposed. Practical relevance. It is proposed to use the developed complex for the creation of identifying flash memory microcircuits intended for statistical research of identification methods and pro-tocols.