Experimental Demonstration of Gate-Level Logic Camouflaging and Run-Time Reconfigurability Using Ferroelectric FET for Hardware Security
Sourav Dutta, Benjamin Grisafe, Chloe Frentzel, Zephan M. Enciso, Matthew San Jose, Jeffrey A. Smith, Kai Ni, Siddharth Joshi, Suman Datta · IEEE Transactions on Electron Devices · 2021
Outsourcing of integrated circuit (IC) manufacturing and increasing sophistication of IC reverse engineering techniques have unleashed security threats such as intellectual property (IP) theft and insertion of hardware Trojans. In this article, we propose and implement a run-time reconfigurable camouflage logic technology based on ferroelectric field-effect transistor (FeFET). The technology simultaneously obfuscates design IP from zero-trust foundry and untrusted testing facility and thwarts reverse engineering and counterfeiting threat. We fabricate for the first time an eight FeFET-based circuit block and demonstratein silicogate-level camouflaging by implementing three Boolean logic functions—NOR, NAND, and XNOR—in the same circuit topology using threshold voltage (${V}_{\text {T}}$) programming of FeFET. We perform circuit simulations using empirically calibrated models to estimate power, latency, and area overhead. Compared with recent proposal of programmable camouflage logic using hot-carrier injection (HCI), FeFET offers an overhead reduction of$2\times $,$1.8\times $, and$2.8\times $in area, power, and delay, respectively.