DSbD CHERI and Morello Capability Essential IP (Version 1)
Robert N. M. Watson, Jonathan D. Woodruff, Alexandre Joannou, Simon W. Moore, Peter Sewell, Arm Limited · CL Technical Reports · 2021
The CHERI protection model extends contemporary Instruction Set Architectures (ISAs) with support for architectural capabilities. The UKRI Digital Security by Design (DSbD) programme is supporting the creation of Arm’s prototype Morello processor, System-on-Chip (SoC), and board. Morello experimentally incorporates the CHERI protection model, developed at the University of Cambridge and SRI International, into the ARMv8-A architecture. This document declares a set of capability essential IP – ideas essential to the creation of a contemporary CHERI capability system in architecture and microarchitecture. Arm and Cambridge agree that they have made this IP available for use without restriction. This document also identifies a set of CHERI background documents that may be of value as prior art.