A Design and Implementation of Adiabatic Logic on Low Power Application Circuits
J Praveen, M. Bhuvanesh, BS Nagarakshitha, Bhanupriya Hk, Ananda Kumar K · Solid State Technology · 2020
The relevant decision of flip-flops topologies is of fundamental significance in the structure ofVery Large Scale Integrated (VLSI) and Complementary Metal-Oxide Semiconductor (CMOS) circuits.Breaking down the conduct of existing customary flip-flops and picking the best flip-flops for thepredetermined application is a fundamental issue to finish the requirement low power circuit. The Dflipflops is the most important block in synchronous counters with excessive power utilization influence thegeneral effectiveness of the system. This power dissipation can be diminished by utilizing the adiabatictechnique. In this paper existing [1-5] flip-flops are designed first, for which delay, power and area arecalculated. Then these existing flip-flops are newly proposed by using an adiabatic technique for whichagain delay, power and area are calculated. The design of these existing and proposed is designed by usingCadence Virtuoso Schematic Editor and Analog Design Environment (ADE) for 180nm technology with asupply voltage of 1.8V and 100MHz frequency. The existing D-flip flop consumes 16.6µW power, but thenewly proposed circuit consumes 1.06µW, which results in power reduced by 93.59%, delays reduced by7.47% and the area remains the same compared to an existing design.