Power Optimization and Power Reduction in RTL Design Using System Verilog Assertion and UVM Technology
C B Veenashree · Zenodo (CERN European Organization for Nuclear Research) · 2020
Power dissipation has now turned into the most basic design limitation. In the design of a SoC, power calculation and examination for the most part comes into picture only after the completion of RTL synthesis. In any case, design optimization for low power is most reasonable before synthesis. After synthesis level the design becomes much more complicated which makes dynamic power targets harder to accomplish. Additionally, changes made later in the design for power optimization lead to cost consumption. It is good to pin point the issue or the bug which is related to power at the beginning itself when they can be still fixed. The methodology for power analysis which is used in this project can be implemented at RTL stage itself. The novel methodology is based on System Verilog assertions to optimize the consumed power of RTL designs. The proposed technique will upgrade the RTL code towards accomplishing low power design. The design will be coded according to the specification and will be integrated into the UVM testbench. The simulation output of UVM testbench shows the mistaken signal, which can be further corrected and power enhancement can be done. The consumed power of the design is significantly reduced as it catches each unused design signal that consumes power.