HPME: A High-Performance Hardware Memory Encryption Engine Based on RISC-V TEE
Tianyu Yin, Guozhu Xin, Jun Shu Han · 2020
Encryption and integrity verification of memory content is very important, especially for IoT devices. In this paper, a high-performance hardware memory encryption engine integrated into RISC-V SoC is proposed. By applying this scheme, we achieved a nearly 41.8% cycle reduction over the reference design. The proposed design can help provide more safety mechanisms for TEE such as Keystone[1] by providing hardware-implemented memory encryption and integrity verification.