AetEC: Adaptive error-tolerant Erasure Coding Scheme Within SSDs
Tianqi Zhan, Xianpeng Wang, Dan Feng, Wei Tong · 2020
Flash memory-based SSDs are popular across a wide range of data storage markets, while the flash memory as a storage medium is becoming increasingly unreliable. To improve reliability, modern SSDs employ many in-device reliability enhancement techniques, such as ECC and RAID. However, existing intra-SSD reliability techniques do not consider both the multilevel reliability problem of flash memory and the imbalance of wear between blocks. Therefore either too much redundancy is provided for low wear blocks, which increases the write amplification, or multiple errors cannot be tolerated for high wear blocks and chips. We proposed AetEC, an adaptive error-tolerant erasure coding scheme within SSDs. AetEC adaptively applies RS (Reed Solomon) erasure codes with different error correction capabilities according to the number of high-wear blocks in the superblock. To tolerate chip-level failures of high-wear blocks, AetEC maximizes the error tolerance of RS codes. To improve performance, AetEC applies the physical address-based stripe organization and implements a FPGA-based RS encoder and decoder. Furthermore, AetEC proposes a double-linked list write cache to both improve write performance and ensure the consistency of user data and check data. We model and analyze the reliability of AetEC on SSDsim. Experiment results show that, compared with the fixed RAID4, the average response time of AetEC is reduced by up to 32.8%, and write amplification is decreased by up to 37.8%. Compared with the latest wear-aware RAID, AetEC reduces the uncorrectable page error rate (UPER) by two orders of magnitude with 5.9% additional response time.