A Bfloat16 Fused Multiplier-Adder
Stafford Hutchins, Earl E. Swartzlander · 2020
This paper describes a new floating-point fused multiplier-adder (FMA) designed for bfloat16 data. Analysis and optimizations for 8-bit exponent logic, adders, and multiplier are presented, and compared in performance and area against a double-precision FMA, and an FMA `scaled' for bloat16 data, where a calculated 19% performance gain with reduced area is achieved over the reference design.