Fair comparison of hardware and software LDPC decoder implementations for SDR space links
Vincent Pignoly, Bertr Le Gal, Christophe Jégo, Benjamin Gadat, Lyonel Barthe · 2020
LDPC codes are a family of error correcting codes used in most wireless and space communication standards such as CCSDS [1] and DVB [2] ones. Thanks to their high error correction features and their parallelism capabilities, different technical solutions nowadays enable their real-time implementations in Software Defined Radio (SDR) contexts. Indeed, even if Error Correction Code (ECC) decoders were previously implemented on dedicated hardware targets (ASIC/FPGA), their real-time implementations on multi-core devices [3]-[5], is now possible. Software implementations currently provide high-throughput and low-latency features, scalability and also flexibility that makes them attractive for SDR systems. However, multi-core power consumption, throughput performance level and prices could be worse compared to ASIC/FPGA solutions for very high-throughput SDR systems. In this paper, a fair comparison of multi-core and FPGA solutions for the development of a 10 Gbps communication system for space communications is detailed.