An Efficient Architecture for 8-point Discrete Hartley Transform Using Parallel Additions
Nibedita Patra, Sudhansu Sekhar Nayak · Solid State Technology · 2020
—In this paper, a simple architecture has been presented for implementation of 8-point DHT. Theimplementation is done mainly by addition operations. The architecture requires only two multipliers withsame constant. The VLSI implementation of the proposed architecture can be done efficiently. The proposedarchitecture provides high throughput of computation