3D NoC emulation model on a single FPGA
Jonathan D'Hoore, Poona Bahrebar, Dirk Stroobandt · 2020
Networks-on-Chip (NoCs) have emerged as a promising solution for the communication crisis in large and highly interconnected Systems-on-Chip. To allow investigating path finding solutions for NoC architectures and provide useful insights into the network design aspects, the performance of the designed NoC needs to be evaluated through simulations/emulations. Although software simulators are flexible and can deliver very accurate results, the simulation time is likely to be prohibitive for large-scale designs. Field Programmable Gate Arrays (FPGAs) can speed up the simulation process significantly, while maintaining the same level of accuracy. However, the FPGA-based NoC emulators proposed so far are mostly limited to 2D NoCs. In this paper, we extend the 2D FNoC emulation model to 3D using a single FPGA. The proposed model takes advantage of 3D Time-Division-Multiplexing (TDM) and a clustering method to be able to emulate large (up to 10,648 nodes) NoCs. In order to acquire an estimate of the resource usage on FPGA, a VHDL implementation is developed for certain sub-modules of the emulator. The resulting estimations are used to determine the optimal clustering size. Furthermore, the accuracy of the proposed model is verified against the well-known BookSim simulator.