A Cache Contention-aware Run-time Scheduling for Power-constrained Asymmetric Multicore Processors
Jian-He Liao, He-Ru Chen, Ya-Shu Chen · 2020
Asymmetric multicore architecture is widely applied to the embedded systems to better trade-off performance and energy consumption. With an increased number of applications concurrently executed in the system, the power consumption and the associated last-level cache latency are increased. To maximize the system performance under the power constraint, we proposed a cache contention-aware run-time scheduling for asymmetric multicore systems. To deal with the dynamic workload and cache contention effect, the CPI model learning is presented to adjust the relation between system performance, executing frequency, and executing clusters. Based on the CPI model prediction, the run-time dispatcher is then presented to determine the executing frequency and cores to maximize system throughput under power constraint. The proposed algorithm was implemented on the commercial Odroid XU4 board. The performance was evaluated using benchmarks and impressive results were obtained.