Low Power Scheduling of Periodic Hardware Tasks in Flash-Based FPGAs
Cornelia Wulf, Michael Willig, Diana Göhringer · 2020
Flash-based FPGAs are well suited for energy aware applications because they are liable to a much lower static energy consumption than SRAM-based FPGAs. The power consumption of Microsemi / Microchip devices is reduced even further due to a low-power mode called Flash*Freeze. Neverthe-less, when many hardware tasks with different idle times share the same FPGA, the applicability of the Flash*Freeze mode is reduced as only the complete FPGA can be put into Flash*Freeze mode. In this paper, a scheduling algorithm called cluster scheduling is introduced that reduces the power con-sumption by clustering periodic hardware tasks and extending Flash*Freeze periods under consideration of real-time constraints. The cluster scheduling algorithm can run standalone or it can be integrated into a real-time operating system. It is evaluated against an algorithm that switches to Flash*Freeze mode whenever the FPGA is idle. Depending on the shifting variability of the hardware tasks, a prolongation of the Flash*Freeze mode in the order of n can be reached with n given hardware tasks.