Mixture of Decimal and Binary Arithmetic Units For FPGA Based Architecture
Satya Ranjan Sahu, Manoranjan Pradhan · 2020
Minimization of rounding error can be done by simply using decimal arithmetic over binary arithmetic systems. This method eliminates the conversion technique which leads to good result. The decimal arithmetic hardware uses a typical binary arithmetic circuit along with a conversion unit. In this proposed architecture BCD input values are divided into many groups of bits to find out the contribution of individual group. The outcome of individual group is to be added to obtain the final output. The paper studies the design of 8 bit grouping mechanism method. The proposed method is simulated using ISim simulator and synthesized using 4vsx35ff668-12 FPGA device. The Delay and device utilization are calculated from the synthesis result and are compared to the earlier conversion technique.