Characterizing the Scale-Up Performance of Microservices using TeaStore
Sriyash Caculo, Kanishka Lahiri, Subramaniam Kalambur · 2020
Cloud-based applications architected using microservices are becoming increasingly common. While recent work has studied how to optimize the performance of these applications at the data-center level, comparatively little is known about how these services utilize end-server compute resources. Major advances have been made in recent years in terms of the compute density offered by cloud servers, thanks to the emergence of mainstream, high-core count CPU designs. Consequently, it has become equally important to understand the ability of microservices to “scale up” within a server and make effective use of available resources. This paper presents a study of a publicly available microservice based application on a state-of-the-art x86 server supporting 128 logical CPUs per socket. We highlight the significant performance opportunities that exist when the scaling properties of individual services and knowledge of the underlying processor topology are properly exploited. Using such techniques, we demonstrate a throughput uplift of 22% and a latency reduction of 18% over a performance-tuned baseline of our microservices workload. In addition, we describe how such microservice-based applications are distinct from workloads commonly used for designing general-purpose server processors. This paper presents a study of a publicly available microservice based application on a state-of-the-art x86 server supporting 128 logical CPUs per socket. We highlight the significant performance opportunities that exist when the scaling properties of individual services and knowledge of the underlying processor topology are properly exploited. Using such techniques, we demonstrate a throughput uplift of 22% and a latency reduction of 18% over a performance-tuned baseline of our microservices workload. In addition, we describe how such microservice-based applications are distinct from workloads commonly used for designing general-purpose server processors.