Apenet+: high bandwidth 3d torus direct network for petaflops scale commodity clusters
Roberto Ammendola, A. Biagioni, O Frezza, Francesca Lo Cicero, A. Lonardo, Pier Stanislao Paolucci, Davide Rossetti, Andrea Salamon, G. Salina, Francesco Simula, Laura Tosoratto, P. Vicini, Infn Tor Vergata, Infn Roma · 2016
We describe herein the APElink+ board, a PCIe interconnect adapter featuring the latest advances in wire speed and interface technology plus hardware support for a RDMA programming model and experimental acceleration of GPU networking; this design allows us to build a low latency, high bandwidth PC cluster, the APEnet+ network, the new generation of our cost-effective, tens-of-thousands-scalable cluster network architecture. Some test results and characterization of data transmission of a complete testbench, based on a commercial development card mounting an AlteraR © FPGA, are provided. 1.