High Level Synthesis of Protocols Described by a Formal Description Technique
Luci Pìrmez, Aloysio C. P. Pedroza, A. Mesquita · 1997
A methodology that efficiently translates Estelle formal specifications into a VHDL description, suitable for High Level Synthesis of communication protocols is proposed. The effect of the protocol description style in VILDL, on the result of the LII. S scheduling step is discussed by report to the Dynamic Loop Scheduling algorithm. An example using a test protocol is given.