Testability Techniques Used in Different Design Environment for Improving Fault Efficiency
Harshi Tomar, Sandeep Sharma, Navaid Zafar Rizvi · 2016
The paper provides an overview of automatic creation of test patterns using different design for testability techniques (DFT). The main intent is to collect the data from specification, design and completely different synthesis environment and then applying various test conditions which aims at to reduce the time required for test case generation and also to relieve the designers from much tedious task. Increasing size and complexity of digital designs has made essential to address critical verification issues at the early stages of design cycle. Therefore, automated verification tools are necessary at higher levels of abstraction. In this context, we have discussed different design for testability techniques for automatically generating test sequence for functional circuits at register transfer level (RTL). These techniques have many advantages and disadvantages so a comparison based on few parameters essential in the circuit is shown to improve the fault efficiency. Experimental results show robustness and reliability of these techniques as compared to other contemporary approaches in terms of fault coverage, fault efficiency, test generation, test application and area overhead. Keywords : Testability Techniques, System on a Chip (SoC), Automatic Test Pattern Generation (ATPG), Design for Testability (DFT) Cite this Article Harshi Tomar, Sandeep Sharma, Navaid Zafar Rizvi. Testability Techniques Used IN Different Design Environment for Improving Fault Efficiency. Recent Trends in Programming languages. 2016; 3(1): 1–6p.