Optimized Design of FIR Filter Based On FPGA
Qihui Fu, Guoqin Zhang, Xiushan Wu, Shubin Yan · Journal of Physics Conference Series · 2020
Abstract Based on the field programmable gate arrays (FPGA), a low area and high speed FIR filter is proposed and designed. The multiplication modules were replaced by adders and shift registers in the proposed architecture. This is possible because a coefficient approximation is performed, using the algorithm that computes the coefficients like a sum-of-powers-of-two (SOPOT). Compared with the traditional method, the area of the 7-tap 12 bit FIR filter occupied is 75%smaller.