Design and Analysis of Clock Fault Injection for AES
Peng Yang, Fang Luo, Qingyu Ou, Dawei Zhou · 2020
Traditional cryptography security often relies on the security of the cryptographic algorithm itself. However, in practice, cryptographic algorithms are always implemented based on software or hardware. In fault attack, attackers induce errors during encryption calculations to extract key information in embedded systems. Clock glitch injection poses a serious threat to cryptographic algorithms, which is a kind of fault attack. This paper proposes a built-in faulty clock generator integrated on FPGA to evaluate fault injection attacks and their impact on encryption modules. The platform generates glitches in a normal clock cycle, and can change the influence range of clock failures by accurately controlling the position and shape of the glitches. The research in this paper shows that the glitch can appear in any assigned cycle, and the width can be adjusted with increments of 0.14ns when the clock cycle is 20ns. This platform has great significance and value for standardizing the failure evaluation process of resource-constrained cryptosystems and building a unified security evaluation framework.