Design of Efficient 1-bit Comparator in Quantum dot Cellular Automata Nano-computing
Suhaib Ahmed, Soha Maqbool Bhat, Vipan Kakkar · 2020
The issues faced by CMOS technology in the nano regime has led to the research of other possible technologies which can operate with same functionalities however with higher speed and lower power dissipation. One such technology is Quantum-dot Cellular Automata (QCA). In this paper, two 1-bit comparator designs using QCA nanotechnology are presented. These designs do not utilize any crossovers and hence can be easily fabricated without any defects. Based on the performance analysis, it is perceived that the proposed comparator designs are highly efficient in respect to cell count, area, delay and quantum cost and achieves performance improvement in the range of 62.91% to 99.67% in terms of quantum cost from the existing comparator designs. Hence, the proposed designs can be efficiently utilized in various digital logics requiring minimal area and ultra-low power consumption such as central processing units (CPUs), microcontrollers, etc.