Mathematical modelling for the design of DFT processor using resource sharing
S. Narendran, J. Manecius Selvakumar · AIP conference proceedings · 2020
In this paper, we have presented a modelling of Discrete Fourier transform (DFT) using resource sharing technique. In our design, we bit sliced the architecture and reduce the computation cost. Since twiddle factor plays a vital role in discrete Fourier transform. This bit slicing technique will reduce hardware cost and improvise speed of the processor. We made a mathematical derivation for N - point Radix - 25Fast Fourier Transform using bit slicing approach by reducing the twiddle factor value. By slicing the 64 - point FFT, we have designed a Superconducting based DFT processor. At which, we reduced the number of multipliers and adders in the design using radix - 25 method. Fast Fourier Transform are used in the applications like spectrum analyzer, signal detector, and a major part in Orthogonal Frequency Division Multiplexing (OFDM) devices. With our modeling approach, we can compute any n2 - point Fast Fourier Transform (FFT).