A 128Gb 1-bit/Cell 96-Word-Line-Layer 3D Flash Memory to Improve the Random Read Latency With tProg = 75 μs and tR = 4 μs
Toshiyuki Kouchi, Mami Kakoi, Noriyasu Kumazaki, Akio Sugahara, Akihiro Imamoto, Yasufumi Kajiyama, Terada Yuri, Sanad Bushnaq, Naoaki Kanagawa, Takuyo Kodama, Ryo Fukuda, Hiromitsu Komai, Norichika Asaoka, Hidekazu Ohnishi, Ryosuke Isomura, Takaya Handa, Kensuke Yamamoto, Yuki Ishizaki, Yoko Deguchi, Atsushi Okuyama · IEEE Journal of Solid-State Circuits · 2020
A 128-Gb 1-bit/cell 3-D flash memory chip has been developed with 96-word-line-layer technology. A novel chip floorplan architecture with less time constants of wordline and bitline realizes fast read access time. A newly introduced program sequence achieves for higher reliability with less read-retry even after write/erase cycles. External VPP supply (12 V), current mode reference distribution, and auto temperature code refresh are also adopted to boost the performance of the chip. A new duty cycle corrector succeeds in obtaining wider unit interval of the DQS. Consequently, the proposed chip has a read access latency of$4~\mu \text{s}$and a program time of 75$\mu \text{s}$, which is 12–13 and 4–5 times faster than conventional 3-D flash memory with the same technology [Maejimaet al., (2018)]. The random read latency (tRRL) is estimated to be less than 50$\mu \text{s}$, which enables in the reduction of total read access time of solid state drive (SSD) system.