Optimization of Memory Oriented Network-on-Chip for FPGA
Rohini Shelke, Ranjit Sadakale · 2020
In this paper we identify that by the bottleneck link interconnect throughput is limited, tons of files gets created automatically in cache and speed of the network becomes slow down also sometimes system gets hang. Hence we are describing Optimization of cache memory by analyzing the Network on chip (NoC) and field programmable gate array. In this paper with the help of ring topology we are introducing the DWT. Discrete wavelet Transform (DWT) is used to compress the cache memory. By implementing this proposed method System will get faster. Using the terms of FPGA, we believe that our implementation system will provide high gain and less intricacy.