FPGA Based Efficient Interface Model for Scale-Free Computer Network using I2C Protocol
P. Venkateswaran, Arindam Sanyal, Snehasish Das, Salil K. Sanyal, Rabindranath Nandi · Research in Computing Science · 2006
Devices communicating with each other over a serial bus must have some protocol to avoid data loss, as well as enabling faster devices to communicate with slower ones. In a network, there may be several electronic modules across which a communication link has to be established. There must be some algorithm to solve conflicts between the contending nodes in the network. In this design, we have implemented an efficient network interface model which can prevent data loss due to collisions. The proposed interface model follows the I2C protocol with a slight change in the manner in which the data transfer is initiated or terminated. The I2C bus is a true multimaster bus which includes arbitration safeguards against data collisions. The interface model described can be used to connect any number of devices to a network