Protecting the FPGA IPs against Higher-order Side Channel Attacks using Dynamic Partial Reconfiguration
Ario Kian, Hamed Hosseintalaee, Ali Jahanian · 2020
Power Attacks have become a serious concern for secure FPGA-based embedded system design. However, considerable countermeasures have been introduced to improve the resistance of FPGA devices against Differential Power Analysis (DPA) and Correlation Power Analysis (CPA) attacks during recent years. In this work, we proposed a novel countermeasure which utilizes the Dynamic Partial Reconfiguration (DPR) property of the FPGA devices to obfuscate the leaked information. DPR capability allows updating a certain part of the running design on the device while other parts remain functioning without interruption. We proposed a new masking scheme using this technology in which masking function is changed dynamically at runtime to violate the assumptions needed for a successful power analysis attack. The proposed method not only overcomes to the first-order DPA attacks but also increases the resistance against the second-order DPA attacks. Our experimental results show that the proposed method has considerable security improvement against first and second order SCA attacks with negligible overheads. Moreover it can be complemented with any other desired countermeasures as well.