CAD for Security: A Full Reverse Engineering Toolchain from Layout to RTL
Yier Jin · 2020
To protect the SoC supply chain from such vulnerabilities, academic and industry researchers have proposed many design for security and hardware Trojan detection techniques. However, these techniques either rely on RTL verification methods which may not be applicable to netlist/layout level designs or leverage testing/measurement results to indirectly identify possible hardware vulnerabilities. There lacks a CAD tool based deterministic process which can convert layouts/netlists into RTL code for design verifications. In this talk, I will introduce our recent effort in building such a CAD toolchain through which a layout in GDS-II format can be de-syntheiszed and converted to the high level description, e.g., RTL code, for security analysis. The CAD toolchain includes a series of circuit reverse engineering tools which can also be applied individually for specific tasks such as design deobfuscation, hardware Trojan detection, etc. This toolchain fits in an even larger concept of CAD for Security, a recent trend for SoC/IC protection and trust verification.