An N × N Multiplier-Based Multi-Bit Strong PUF using Path Delay Extraction
Chongyao Xu, Jieyun Zhang, Man‐Kay Law, Xiaojin Zhao, Pui‐In Mak, Rui Paulo Martins · 2020
This paper presents a digital N × N multiplier-based multi-bit strong physical unclonable function (PUF), which utilize the intrinsic path delay of the multiplier to achieve an approximated 1 : 2N2average challenge-to-response extraction to effectively increase the number of PUF responses. The PUF Extractor triggers the digital multiplier, and further processes the multiplier intrinsic path delay through a time-to-digital converter (TDC). Implemented with Xilinx Artix-7 FPGAs using the automatic place and route function, the proposed strong PUF demonstrates a 64-bit challenge with 32-bit multipliers with an extra level of unpredictability for counterfeiting model-based machine learning attack. With an average of 1:2048 responses per challenge, measurement results show that the uniqueness is 53.16%, and the stability of up to 95.54%, respectively.