An FPGA Implementation of Arbiter PUF with 4x4 Switch Blocks
Can Aknesil · KTH Publication Database DiVA (KTH Royal Institute of Technology) · 2020
Theft of services, private information, and intellectual property have become significant dangers to the general public and industry. Cryptographic algorithms are used for protection against these dangers. All cryptographic algorithms rely on secret keys that should be generated by an unpredictable process and securely stored. The keys are usually stored in a memory, e.g. Flash or fuses. Therefore, the strength of cryptographic protection relies upon the ability of an attacker to extract the keys from the hardware. Modern hardware implementation methods are very advanced, weakening cryptographic algorithms against physical attacks. Finally, memories that provide extra security are expensive to be used in Integrated Circuits (ICs). As a solution to the memory key storage problem, Physically Unclonable Functions (PUFs) have been proposed. A PUF is an electronic circuit that evaluates responses of hardware to given input stimuli. Due to manufacturing process variations, every IC has different characteristics at the analog level. These variations lead to measurable differences, hence different responses of PUFs implemented on different IC chips. In this thesis, we are implementing recently proposed 4 x 4 Arbiter Physically Unclonable Function (APUF) on Field-Programmable Gate Arrays (FPGAs), performing statistical analysis including uniformity, reliability, and uniqueness, comparing hardware overhead of our FPGA design to other APUF variants, providing a mathematical model using homogeneous coordinates, and proposing methods that enable usage of our PUF in real-world applications. We selected this particular type of PUF because it is claimed to be more area efficient than its alternatives while providing strong security and reconfigurability. According to our analysis, the presented 4 x 4 APUF design is suitable for many security applications, including identification, authentication, encryption, and key generation. Furthermore, its FPGA area is considerably smaller than the area of 2 x 2 APUF variants accepting challenges of the same size. However, since uniqueness of our design is lower than desirable, to be used in security applications, our PUF requires repeated invocations and generation of larger keys by combining many responses, thus additional computation during runtime.