From 2D to 3D Nonvolatile Memories
Akira Goda · 2020
The NAND architecture has been leading nonvolatile memories in both the technology scaling and the market size. The 4 bits per cell technology has been realized in 3D NAND, which further enhances the bit cost scaling in 3D NAND. In a 2D NAND string, memory cells are arranged in series between select gates. The principle of the technology scaling is different between 2D NAND architecture and 3D NAND architecture. In the 2D NAND, the cell density was increased by reducing the physical cell size. The cell-to-cell interference increases in the scaled 2D NAND when the cell becomes smaller and the distance to the neighboring cells becomes shorter. Polysilicon is used for the channel in 3D NAND due to the requirements from process integration. The 3D NAND cell shows improved electrical characteristics compared to the scaled 2D NAND cell thanks to a larger cell size and a GAA cell structure.