A Novel Design Reversible Logic Based Configurable Fault-Tolerant Embryonic Hardware
Kasem Khalil, Bappaditya Dey, Yasser Sherazi, Ashok Kumar, Magdy Bayoumi · 2020
With the advancement of advanced node technology beyond sub-10 nm nodes, high-performance computing is facing a great challenge in the form of excessive levels of heat. Against this limitation, we can re-synthesis any complex digital circuits using reversible logic only, known for ideally Zero-heat dissipation. This paper proposes a novel reversible logic based on Configurable Fault-Tolerant Embryonic Hardware. We have reinvestigated the concept of Self-healing for hardware systems in the context of reversible logic and circuits. This paper presents a comparative analysis between conventional and proposed quantum approach on various parameters such as area-overhead, power dissipation and quantum cost along with the limitations of conventional computing. The reliability of the proposed approach is analyzed against other existing classical approaches with different failure rates. The overall power dissipation is almost 19% lower for the proposed approach compared to other conventional approaches using digital gates with cell number 32. The proposed approach is implemented for the ALU array using VHDL on Altera 10 GX FPGA.