A Novel Both-Sided Bitline Driving Technique for Low Latency in High Capacity NAND Flash
Jun Ho An, Hyunkook Park, Tae Woo Oh, Seong‐Ook Jung · 2020
High capacity design in NAND Flash has become one of the important issues due to increasing demand for memory capacity expansion. As the number of blocks in NAND Flash increases for high capacity, the driving time of bitline (BL) increases with a large RC, which should be resolved for high capacity NAND Flash. This paper proposes a both-sided BL driving scheme (BSBLDS) for high capacity NAND Flash to achieve a fast driving operation by using an area-optimal NMOS at the far side of the BL. In the conventional one-sided BL driving scheme, the BL driving takes a long time because the current of the BL far node is significantly smaller than that of the BL near node. In the proposed BSBLDS, the both-sided BL overdriving and discharging modes are respectively implemented for fast precharge and discharge operations. The proposed BSBLDS achieves 180% faster precharge speed and 190% faster discharge speed than the conventional driving scheme.