Design and Analysis of Low Power Reversible Adder/Subtractor Circuits
Nitin Krishna V · International Journal of Engineering Research and · 2020
In recent years, reversible logic has become a promising technology in the areas of low power VLSI design, nanotechnology, quantum computing and optical computing.The performance and reliability of digital systems which are now implemented using conventional logic gates can be enhanced by the usage of reversible logic gates, which pave for low power consumption and lesser quantum delays, thus increasing the speed of computation.Adder/subtractor circuits form the fundamental block in the arithmetic and logic unit of processors and other digital logic programmable devices.The performance of a digital system, its speed and throughput depend critically on the way these circuits are designed.Adder circuits are used in the Graphics Processing Unit(GPU) of computers for graphics applications to reduce complexity.Any way to enhance the performance and computational speed of these circuits will pave way for a better ALU.Incorporating the concepts of reversible computing in the design of adder/subtractor circuits can significantly enhance the performance and speed of operation of digital systems.In this paper, two existing adder/subtractor designs and a novel design are compared, analyzed for different bit lengths (1,8,16,32,64).Detailed analysis of reversible logic design parameters, power consumption parameters, and FPGA utilization parameters is carried out.These designs are analyzed and simulated using the Xilinx Vivado tool and implemented on Zedboard Zynq 7000 Evaluation and Development kit(xc7z020clg484-1). The proposed design outperforms the existing designs.