A Robust CTS algorithm using the H-Tree to minimize local skews of higher frequency targets of the SOC designs
P. Bhaskara, P.V.S.R. Bharadwaja · 2020 7th International Conference on Smart Structures and Systems (ICSSS) · 2020
The high frequency requirements of the current day spec. Because of the logical levels, functionality and latency values are causing a huge impact on the timing. Meeting the timing is becoming a hard task for the recent higher frequency designs. This timing is heavily impacted because of the CTS strategy. So in Physical Design CTS has playing a major role in delivering the high frequencies chips into the market. We propose practical ASIC strategies including the different test case techniques for the flexible building of a clock strategy which is called “H-Tree with local skews”. By taking care of the SI, crosstalk and DRVs we are going to build a robust strategy covering the area and power.