An M-Cache-Based Security Monitoring and Fault Recovery Architecture for Embedded Processor
Xiang Wang, Zongmin Zhao, Dongdong Xu, Zhun Zhang, Qiang Hao, Mengchen Liu · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2020
Recently, extensive research attention has been drawn to the program executing security of embedded processor since increasing code tamper attacks, as well as transient faults severely affect the safety of embedded systems. The security monitoring and fault recovery technique is one of the effective methods to ensure the security and performance of embedded devices. In this article, an architecture for the security monitoring and fault recovery is proposed for run-time program execution, which builds a Monitoring Cache (M-Cache) and then checks the integrity based on reference data. Especially, the proposed architecture will build the checkpoint once the M-Cache is missed and also take the rollback operation after the unsuccessful of integrity check. In addition, three tampered positions (e.g., instruction register within the pipeline, instruction within the cache, and code within memory) have been elaborately focused on to guarantee the normal running of the embedded system. Eventually, by adopting the open RISC processor for algorithm implementation and verification, the proposal has been proven to be promising for the detection of a fault or tampered program, as well as the fast recovery of running environment and code.