An Efficient Sorting Architecture for Area and Energy Constrained Edge Computing Devices
Amin Norollah, Zahra Kazemi, Hakem Beitollahi · 2019
Some edge devices take the advantages of hardwareassistant modules to implement basic computations e.g., sort, addition, etc out of the processor to let the processor show a better performance. However, existing hardware implemented sorting architectures are not good fit for edge computing applications where we need high performance efficiency while cannot afford high area and energy consumption. In this paper, we design and evaluate a sorting architecture for edge computing devices. The proposed architecture is based on the Bitonic sorting algorithm and performs parallel Compare-And-Swap (CAS) operations to sort the input data series. This paper presents a new sorting architecture that reduces the number of hardware resources and energy consumption compared to the state-of-the-art sorting architecture and achieves the desired performance using Unary processing. Our synthesis results by Xilinx Vivado tool indicate that the proposed architecture increases throughput by 29.1% and reduces the number of hardware resources by 42%, for an 8-input sorting architecture which is a remarkable energy saving for edge component.