Reconfigurable Hardware Design for Polynomial Galois Field Arithmetic Operations
Hariveer Inumarty, M. Mohamed Asan Basiri · 2020
Galois Field (GF) arithmetic plays an important role in cryptography algorithms and their numerous applications in communications, signal processing, and security. There is scope for optimizing these arithmetic circuits. In this paper, we consider a reconfigurable digital circuit which performs various GF arithmetic operations with the same set of hardware. Using this hardware we can perform a few operations in parallel. The throughput of the proposed design is greater than various existing techniques. Also, our proposed approach reduces the cost of the hardware, where instead of using all the GF arithmetic circuits we can replace with this proposed hardware. The proposed design has the critical path delay of 25.59 ns using Artix 7 FPGA implementation. Also, our proposed design achieves 83% of improvement in the throughput than the direct form based GF(216) multiplier.