Custom-IP for Gradient Descent Optimization based on Hardware/Software Co-design Paradigm
B B Shabarinath, P. Muralidhar · 2020
Field Programmable Gate Arrays (FPGA's) are being deployed in cloud data centers like Amazon Elastic compute cloud F1 instances for algorithmic acceleration to leverage the advantage of reconfigurability combined with high throughput and low power consumption of FPGA's and hence balancing the dynamic workloads. Gradient Descent is one such algorithm that is extensively used in core computation kernels to train the Machine Learning (ML) models. This paper proposes a custom-IP (Intellectual Property) for hardware acceleration of Gradient Descent Algorithm (GDA) which is designed by exploring the inherent concurrency of GDA. The IP incorporates the Very High-Speed Integrated Circuit Hardware Description Language (VHDL) based description of GDA and AXI4 stream interface for connectivity. The Custom-IP is flexible and reusable by tuning generics defined in the VHDL code. The IP is interfaced to a 32-bit MicroBlaze soft-core processor which acts as host and manages run-time along with other peripherals to form a System on Chip (SoC) in which the design is partitioned into fixed hardware and flexible software. The Hardware/Software Codesign results show the 5x improvement in performance when implemented on Artix XC7A100T-CSG324 FPGA when compared to software implementation.