A Flexible Precision Multi-Format In-Memory Vector Matrix Multiplication Engine in 65 nm CMOS With RF Machine Learning Support
Mandovi Mukherjee, Yun Long, Jongseok Woo, Daehyun Kim, Nael Mizanur Rahman, Saurabh Dash, Saibal Mukhopadhyay · IEEE Solid-State Circuits Letters · 2020
An all-digital flexible precision in-memory accelerator for vector matrix multiplication (VMM) is demonstrated in 65 nm CMOS. The design supports flexible precision, floating point, and complex numbers enabling in-memory radio-frequency machine learning and signal processing computation. The measured compute efficiency normalized to memory size is 34 GOPS/W/KB.