High-Performance Solid State Drive with Parallel Read Scheme
A. L. Berman · 2020
NAND Flash memory is widely used for data storage in electronic products, and especially in mobile devices. The high demand for denser memory is approached by monolithic 3D cell placement, along with multiple bits per cell (Multi-Level-Cell or MLC) architectures. In this paper, we suggest a method to improve the read latency of NAND flash memories using MLC architectures. The conventional read flow consists of the following steps: 1. Sensing: sequential comparisons of a wordline's cell voltage threshold (VT) to a reference value, an action that takes place inside the NAND chip. 2. Data transmission: transmitting the decoded binary data from the NAND chip to the memory controller over a shared bus. We have observed that the temporary sensed binary vectors are often sparse and, therefore, can be compressed efficiently. We propose a method that sends the temporary sensed data to the target controller in parallel while executing the next reference comparison. The NAND read process is re-ordered such that the smallest block is the last to be transmitted, so that bus usage after the final NAND sensing is reduced. Our analysis shows that in 8-levels MLC, read latency is reduced by 25%. In the case of ZNAND's 1μs sensing (or emerging memory), the savings increase to more than 50%. Our method is scalable as acceleration grows with more bits per cell or larger page size.