Enabling hardware randomization across the cache hierarchy in Linux-Class processors
Max Doblas, Ioannis-Vatistas Kostalampros, Miquel Moretó, Carles Hernández Luz · UPCommons institutional repository (Universitat Politècnica de Catalunya) · 2020
The most promising secure-cache design approaches use cache-set randomization to index cache contents thus thwarting cache side-channel attacks. Unfortunately, existing randomization proposals cannot be sucessfully applied to processors’ cache hierarchies due to the overhead added when dealing with coherency and virtual memory. In this paper, we solve existing limitations of hardware randomization approaches and propose a cost-effective randomization implementation to the whole cache hierarchy of a Linux-capable RISC-V processor.