Reversible Logic Implementation of Image Denoising for Grayscale Images
Sithara Raveendran, Pranose J. Edavoor, Y. B. Nithin Kumar, Moodabettu Harishchandra Vasantha · 2020
Reversible logic has emerged as a solution for the limit set by power consumption of devices on reduction of transistor size. This paper aims at introducing reversible logic based implementation for image processing units. A image denoising module is implemented using reversible logic gates. Gray equivalent of an RGB input is processed using a mean filter to remove the noise present in the images. Mean filter with spatial window size of 2×2 and 4×4 is implemented. The verification of functionality is carried out on Kintex 7 using Verilog. The architectures are analysed in terms of power consumption and hardware utilised. The reversible logic implementation is done and the efficacy is measured in scales of gate count(GC), ancilla inputs(AI), quantum cost(QC) and garbage output(GO). The proposed work can act as the initial blocks in image compression algorithm implementations in reversible logic.