Implementation of Multi Spin-Thread Architecture to Fully-Connected Annealing Processing AI Chips
Ryoma Iimura, Satoshi Kitamura, T. Kawahara · 2020
Artificial intelligence (AI) processing on edge computing in the Internet of Things (IoT) society requires our focus on the Ising model to enable advanced information processing with low-power consumption, small area, and thorough implementation in LSI chips. The configuration is such that the fully-connected interaction layer (memory) and the spin and calculation layers of the Ising model are separated and directly connected in parallel. A stochastic operation is performed in the Ising model because annealing is used to obtain a solution. However, an optimal solution cannot always be obtained using one calculation. Therefore, we devised and implemented the concept of a multi spin-thread by taking advantage of the fact that multiple spin sets and calculation layers are possible. In the multi spin-thread, multiple threads can be calculated simultaneously with spin required for calculation being one thread. Therefore, the state of the other spin-threads can be adjusted to the state of the spin-thread with the smallest Hamiltonian, and a state with a lower Hamiltonian can be searched. This improves the accuracy of the solution. A 28-nm CMOS LSI (AI chip) with 512 spins and eight spin-threads was tested. In a 22-city traveling salesman problem (TSP), the average path length could be reduced by 19% and the dispersion reduced by 70% on average, and the number of cuts in the 512-node max-cut problem could be increased by 1.6% on average and the dispersion reduced by 84%. The time required to obtain the solution was 128 ms.