Efficient Hardware Design Architectures for BCH Product Codes in the Frequency Domain
Arijit Mondal, Shayan Srinivasa Garani · 2020
We propose efficient encoding and decoding hardware architectures for (n, k), t-error correcting Bose-Chaudhuri-Hocquenghem (BCH) product codes in the frequency domain. Using the properties of conjugate classes over a finite field, we reduce the algorithmic complexity of the encoder, leading to a significant reduction in the hardware complexity. A low latency (2t+2) decoder for the above encoder is also designed. For a particular case of n=15 and t=2, the architectures were implemented on a Kintex 7 KC-705 FPGA kit, giving high throughputs of 22.5 Gbps and 5.6 Gbps at 100 MHz for the encoder and decoder respectively.