Single Wire Debug Interface
Bhanu Pratap Singh, Sharath Patil · 2020
The JTAG IEEE 1149.1 standard specifies a fourpin test access port and an optional test reset pin as a debug interface for a chip. In this paper, we propose a single wire debug (SWD) interface for an existing IEEE 1149.1 compliant device. The proposed SWD design requires only one pin and can be integrated into severely pin-limited ICs, where only a few package pins are available for debugging. This reduction in pin count has advantages in terms of miniaturization and packaging cost reduction. SWD can be used to debug and trace functionality on ARM7 and ARM9 class of processor cores from ARM Ltd. using JTAG in-circuit emulators.