Towards achieving an 100-hour design cycle : a test case
Daniel D. Gajski, Loganath Ramachandran, Peter Fung, Frank Vahid, Sanjiv M. Narayan · eScholarship (California Digital Library) · 1994
With recent success in logic synthesis tools, many designers are focussing on capturing the design with a Register Transfer Level (RTL) description and using synthesis tools to complete the rest of the design. Due to the large amount of detail, writing a RTL description requires a long time, making it unacceptable when designs have to be produced rapidly. In this paper we propose a design methodology that can shorten the design cycle significantly. This is achieved by specifying the design at the highest level of abstractions and using powerful tools to complete the rest of the design. We have used this methodology on an industrial application, where we have designed and implemented a fuzzy logic controller.