An Ultra-Low Latency 7.8–13.6 pJ/b Reconfigurable Neural Network-Assisted Polar Decoder with Multi-Code Length Support
Chieh-Fang Teng, Chun‐Hsiang Chen, An-Yeu Andy Wu · 2020
To meet with the stringent requirements of ultra-low latency communication in 5G, this work presents a polar decoder fabricated in TSMC 40nm CMOS featuring: 1) World's first neural network-assisted decoder chip with 8× improvement of convergence rate. 2) Fully reconfigurable architecture to support multi-code length operations with a 2-to-8× hardware utilization rate. 3) Optimized fixed-point design of processing element (PE) to reduce 73% area and 67% power consumption.