LOW PASS IIR FILTER DESIGN ON POSIT NUMBERS FORMAT USING VERILOG
Kamel Alikhan Siddiqui, Amairullah Khan Lodhi, Mohammad Ilyas · Journal of Critical Reviews · 2020
Designing of IIR filter is one of the complex tasks and an essential Digital component for the present high precision technology of era on 120 nm Technology of todays no Time to Market world. The augmented usage of filters is highly unstoppable and needless to mention in the ever-changing demand of Digital versatility. With the inclusion of new word format apart from Fixed Point and Floating point which can play an important role in increasing the resolution, accuracy, and Dynamic range for representation has been introduced. This new impact of a word size is Posit Numbers of the UNUM-iii category (1). The architectural Algorithm of such filter including an Adder, Subtraction, Multiplier, and Divisor along with the Logarithmic and Trigonometric function play a vital role in efficient Filter design with efficient algorithm has been implemented in FPGA with proper Data Path design that develops a new and unique categorical study for several many more implementation and prototypes. The abstract also showers light on the Verilog domain for the presentation of the Data path design and Posit number Extracting, Detecting, Shifting, Rounding, and lastly packaging for presentation for various arithmetic operations.