Automatic Identification and Precise Attribution of DRAM Bandwidth Contention
Christian Helm, Kenjiro Taura · 2020
The limited DRAM bandwidth of today’s computing systems is a bottleneck for many applications. But the identification of DRAM bandwidth contention in applications is difficult. The measured bandwidth consumption of an application can not identify bandwidth contention. In theory, NUMA systems can provide higher memory bandwidth. But applications often make poor use of the resources. To address these challenges, we introduce a novel method to identify DRAM bandwidth contention and bad usage of NUMA resources. It consists of metrics to judge the severity of bandwidth contention and the degree of imbalanced resource usage in NUMA systems. Our tool can automatically scan an application for DRAM contention problems. Together with the precise location of the origin, intuitive optimization guidance is given. This approach for finding DRAM contention is based on the memory access latency. By comparing the experienced latency of an application with the uncontended hardware latency, we can find the contention. Hardware instruction sampling enables precise identification of the origin. It also provides information about accessed memories, which we use to calculate a NUMA imbalance metric. In a detailed evaluation with several micro-benchmarks, we show that our new method does indeed quantify the severity of DRAM contention beyond the possibilities of simple bandwidth consumption measurement and existing tools. We also apply our approach to real applications and confirm that it gives useful optimization advice to users.